Device structures with dual layers of polysilicon over oxide layers of differing thickness have many uses in integrated circuits such as Dynamic Random Access Memory (DRAM) cells, Static Random Access Memory (SRAM) cells, etc. The process for manufacturing dual-polysilicon structures currently requires multiple polysilicon depositions, patterning, and etches. Each deposition, patterning, and etch sequence is both time consuming and costly.
Additionally, the multi-layered polysilicon structure produced by such a known process yields an uneven topology upon which further processing steps must typically be performed. Carrying out further steps on such an uneven topology can be difficult.